Formally embedding existing high level synthesis algorithms

نویسندگان

  • Dirk Eisenbiegler
  • Ramayya Kumar
چکیده

This paper introduces a general scheme for formally embedding high level synthesis by formulating its basic steps as transformations within higher order logic. A functional representation of a data ow graph is successively reened by means of generic logical transformations. Algorithms that are based on logical transformations guarantee \correctness by design". They not only construct an implementation but also derive the proof for its formal correctness, on the y. An extra post-synthesis-veriication step becomes obsolete. The logical transformations presented in this paper form a framework for formally embedding existing high-level-synthesis procedures.

برای دانلود متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

ثبت نام

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

منابع مشابه

Implementation Issues About the Embedding of Existing High Level Synthesis Algorithms in HOL

This article describes the embedding of high level synthesis algorithms in HOL. For given standard synthesis steps, we describe, how its data can be mapped to terms in HOL and the synthesis process be expressed by means of a logical derivation. In contrast to post-synthesis ver-iication techniques our approach is constructive in a sense that the proof is derived during synthesis rather than \gu...

متن کامل

Link Prediction using Network Embedding based on Global Similarity

Background: The link prediction issue is one of the most widely used problems in complex network analysis. Link prediction requires knowing the background of previous link connections and combining them with available information. The link prediction local approaches with node structure objectives are fast in case of speed but are not accurate enough. On the other hand, the global link predicti...

متن کامل

A Formally Veri ed High-Level Synthesis Front-end: Translation of VHDL to Dependence Flow Graphs

We show that it is feasible to verify parts of a high-level synthesis system by giving semantics to the representation languages used and showing that the algorithms produce designs with meanings that reene their speciications. Previous eeorts attempting to relate hardware veriication techniques and high-level synthesis have concentrated on showing that the individual designs produced by synthe...

متن کامل

Modeling the Global Critical Path in Concurrent Systems

We show how the global critical path can be used as a practical tool for understanding, optimizing and summarizing the behavior of highly concurrent self-timed circuits. Traditionally, critical path analysis has been applied to DAGs, and thus was constrained to combinatorial sub-circuits. We formally define the global critical path (GCP) and show how it can be constructed using only local infor...

متن کامل

A Model for Buffer Exploration in EDF Scheduled Embedded Systems

The present paper describes an extension to real-time analysis of earliest-deadline first (EDF) scheduled embedded systems to allow design space exploration with different intertask communication. The event stream approach for real-time analysis is generalized to unbuffered task communication. Adding this analysis technique to a well known cost model for system level synthesis, it becomes possi...

متن کامل

ذخیره در منابع من


  با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید

برای دانلود متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

ثبت نام

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

عنوان ژورنال:

دوره   شماره 

صفحات  -

تاریخ انتشار 1995